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Chapter 2
Programmer’s Model
This chapter describes the ARM926EJ-S registers in CP15, the system control
coprocessor, and provides information for programming the microprocessor.

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Table 2-18 Cache operations c7
Function/operation Data format Instruction
Invalidate ICache and DCache SBZ MCR p15, 0, Rd> c7, c7, 0
Invalidate ICache SBZ MCR p15, 0, Rd, c7, c5, 0
Invalidate ICache single entry (MVA) MVA MCR p15, 0, Rd, c7, c5, 1
Invalidate ICache single entry (Set/Way) Set/Way MCR p15, 0, Rd, c7, c5, 2
Prefetch ICache line (MVA) MVA MCR p15, 0, Rd, c7, c13, 1
Invalidate DCache SBZ MCR p15, 0, Rd, c7, c6, 0
Invalidate DCache single entry (MVA) MVA MCR p15, 0, Rd, c7, c6, 1